simd-anim

Instruction lab

simd-anim

A small static lab that animates real SIMD and SME instructions — then shows how they compose into kernels, and what decides a kernel's speed.

New to matrix multiply? Take the optional self-check

Instructions

One page per instruction, each animating the data it moves.

  1. 01 SME · Live

    FMOPA

    Outer product of z0.s and z1.s, accumulated into a 4×4 ZA tile.

    Play this instruction

    fmopa za0.s, p0/m, p1/m, z0.s, z1.s
  2. 02 SVE · Live

    Vector load / pack

    Bring memory into a Z register, lane by lane, then pack those lanes.

    Play this instruction

    ld1w { z0.s }, p0/z, [x0]
  3. 03 SVE · Live

    FMLA

    A fused multiply-add along a predicated vector.

    Play this instruction

    fmla z0.s, p0/m, z1.s, z2.s
  4. 04 SME · Live

    Store

    Write one horizontal slice of a ZA tile back to memory.

    Play this instruction

    st1w { za0h.s[w12, 0] }, p0, [x0]
  5. 05 SVE · Live

    WHILELT

    Turn scalar bounds into a predicate: lane i is active while x0 + i < x1.

    Play this instruction

    whilelt p0.s, x0, x1
  6. 06 SVE · Live

    ADDV

    Collapse the active lanes of a vector into one scalar sum.

    Play this instruction

    uaddv d0, p0, z0.s
  7. 07 SVE · Live

    UZP1

    Deinterleave: the even elements of two vectors gather into one.

    Play this instruction

    uzp1 z0.s, z1.s, z2.s
  8. 08 SVE · Live

    Gather load

    Each lane reads the word its own vector index selects — duplicates included.

    Play this instruction

    ld1w { z0.s }, p0/z, [x0, z1.s, sxtw #2]
  9. 09 SME2 · Live

    FMLAL

    Half-precision operands, single-precision tile: a widening multiply-add with an indexed vector.

    Play this instruction

    fmlal za.s[w11, 4:5], z0.h, z1.h[2]
  10. 10 SME · Live

    ADDHA

    One vector lands in every active row of the ZA tile.

    Play this instruction

    addha za0.s, p0/m, p1/m, z0.s
  11. 11 SVE · Live

    TBL

    Each lane picks any element of an eight-entry table — out of range gives zero.

    Play this instruction

    tbl z0.s, { z1.s, z2.s }, z3.s

Kernels

Instructions composed into a whole that computes.

  1. 01 SME · Live

    Microkernel

    How pack, the K loop, and the store compose a real GEMM kernel — in every transpose state.

    Play this kernel

    pack → ldr + fmopa ×2 → st1w / stnt1w

Strategy

The machine-level ideas — how data supply, reuse and latency decide what a kernel can reach.

  1. 01 Hardware · Live

    The hardware

    A register, the ZA tile, and the compute unit — three names every other page uses.

    Open this page

    Z · ZA · ×+
  2. 02 Performance model · Live

    Roofline

    Why reuse, not just FLOPs, decides speed — the memory wall in one picture.

    Open this page

    performance = min(peak, supply × intensity)
  3. 03 Cache choreography · Live

    Memory in flight

    Prefetch and store traffic across two kernels, level by level — and the one slot where HBM reads and writes collide.

    Open this page

    pldl2keep / pldl1strm / stnt1w — across kernels

Words this lab uses

The four abbreviations, spelled out once so no page has to repeat them.

SVE
Scalable Vector Extension — the vector half of the ISA, where the z registers and p predicates come from.
SME
Scalable Matrix Extension — adds the ZA matrix accumulator and the outer-product instructions (fmopa, addha, st1w).
SVL
Streaming vector length — how many bits one vector holds, fixed by the hardware; 128 in every drawing here.
ZA
The SME matrix accumulator — the square tile that fmopa accumulates into and st1w writes back to memory.