simd-anim
All instructions

02 SVE · vector load

LD1W

Contiguous words walk from memory into z0.s; lanes whose predicate bit is 0 are filled with zero.

Instruction
ld1w { z0.s }, p0/z, [x0]

Types: z0.s — 32-bit float, 4 lanes; every mem word is 32 bits. Drawn at SVL = 128 bits, so the window is 16 bytes; at SVL = 512 it would be 16 lanes and 64 bytes.

mem

[x0]5
[x0,#4]7
[x0,#8]2
[x0,#12]9
[x0,#16]6
[x0,#20]4

p0/z

z0.s

3 1 4 2

z0.s ← mem[x0, 4]

Ready. z0.s still holds the values it had before this load.

Arrow keys step, space plays or pauses.

Reading the picture

  1. Contiguous addressing

    Element i loads from x0 + 4 × i: one word per .s lane, walking memory in order. Four active lanes cover exactly sixteen bytes.

  2. Zeroing with /z

    Loads take /z, not /m: an inactive lane is written with 0 instead of keeping its old value. Click a predicate bit and watch that lane reset to zero. Compare with FMLA and FMOPA, which merge.

  3. No stray reads

    Predicated-off elements cause no memory access at all. The dimmed words at [x0,#16] and [x0,#20] are never touched, no matter what they hold.

This pass reads {5, 7, 2, 9} and overwrites z0.s = {3, 1, 4, 2}.